H8SLASH3028F datasheet(697/923 Pages) RENESAS

697 / 923 page

Rev. 2.00, 09/03, page 667 of 890

Condition

f = 2 M to 25 MHz

Item

Symbol

Min

Max

Unit

Test Conditions

Bus request setup time

tBRQS

—

Figure 21.16

Bus acknowledge delay

time 1

tBACD1

—30

Bus acknowledge delay

time 2

tBACD2

—30

Bus-floating time

tBZD

—30

RAS precharge time

tRP

1.5 tcyc – 25

—

CAS precharge time

tCP

0.5 tcyc – 15

—

Row address hold time

tRAH

0.5 tcyc – 15

—

RAS delay time 1

tRAD1

—25

Figure 21.17 to

figure 21.19

RAS delay time 2

tRAD2

—30

CAS delay time 1

tCASD1

—25

CAS delay time 2

tCASD2

—25

WE delay time

tWCD

—25

CAS pulse width 1

tCAS1

1.5 tcyc – 20

—

CAS pulse width 2

tCAS2

1.0 tcyc – 20

—

CAS pulse width 3

tCAS3

1.0 tcyc – 20

—

RAS access time

tRAC

—

2.5 tcyc – 40

Address access time

tAA

—

2.0 tcyc – 50

CAS access time

tCAC

—

1.5 tcyc – 50

WE setup time

tWCS

0.5 tcyc – 20

—

WE hold time

tWCH

0.5 tcyc – 15

—

Write data setup time

tWDS

0.5 tcyc – 20

—

WE write data hold time

tWDH

0.5 tcyc – 15

—

CAS setup time 1

tCSR1

0.5 tcyc – 20

—

CAS setup time 2

tCSR2

0.5 tcyc – 15

—

CAS hold time

tCHR

0.5 tcyc – 15

—

RAS pulse width

tRAS

1.5 tcyc – 15

—

Signal rise time (all input

pins except EXTAL)

tSR

—

100

Figure 21.28

Signal fall time (all input

pins except EXTAL)

tSF

—

100

Note: In order to secure the address hold time relative to the rise of the

RD strobe, address

update mode 2 should be used. For details see section 6.3.5, Address Output Method.

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