H8SLASH3028F datasheet(816/923 Pages) RENESAS

816 / 923 page

Rev. 2.00, 09/03, page 786 of 890

DTCR0B—Data Transfer Control Register 0B (cont)

H'FFF2F

DMAC0

• Full address mode

Bit

Initial value

Read/Write

R/W

DTME

R/W

—

R/W

DAID

R/W

DAIDE

R/W

TMS

R/W

DTS2B

R/W

DTS1B

R/W

DTS0B

Data transfer select 2B to 0B

Bit 2

DTS2B

Bit 1

DTS1B

Bit 0

DTS0B

Data Transfer Activation Source

Normal Mode

Block Transfer Mode

Auto-request

(burst mode)

Not available

Auto-request

(cycle-steal mode)

Not available

Falling edge input of

DREQ

Low level input at

DREQ

Compare match/input

capture A interrupt from

16-bit timer channel 0

Compare match/input

capture A interrupt from

16-bit timer channel 1

Compare match/input

capture A interrupt from

16-bit timer channel 2

A/D converter conversion

end interrupt

Not available

Falling edge input of

DREQ

Not available

Transfer mode select

Destination is the block area in block transfer mode

Source is the block area in block transfer mode

Destination address increment/decrement (bit 5)

Destination address increment/decrement enable (bit 4)

Bit 5

DAID

Bit 4

DAIDE

Increment/Decrement Enable

MARB is held fixed

Incremented: If DTSZ = 0, MARB is incremented by 1 after each transfer

If DTSZ = 1, MARB is incremented by 2 after each transfer

MARB is held fixed

Decremented: If DTSZ = 0, MARB is decremented by 1 after each transfer

If DTSZ = 1, MARB is decremented by 2 after each transfer

Data transfer master enable

Data transfer is disabled

Data transfer is enabled

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