H8SLASH3028F datasheet(854/923 Pages) RENESAS

854 / 923 page

Rev. 2.00, 09/03, page 824 of 890

SSR—Serial Status Register

H'FFFB4

SCI0

Bit

Initial value

Read/Write

R/(W)*

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FER/ERS

R/(W)*

PER

TEND

MPB

R/W

MPBT

Transmit end (for serial communication interface)

Multiprocessor bit transfer

Multiprocessor bit value in transmit data is 0

Multiprocessor bit value in transmit data is 1

Multiprocessor bit

Multiprocessor bit value in receive data is 0

Multiprocessor bit value in receive data is 1

[Clearing conditions]

• Read TDRE when TDRE = 1, then write 0 in TDRE.

• The DMAC writes data in TDR.

[Setting conditions]

• Reset or transition to standby mode

• TE is cleared to 0 in SCR.

• TDRE is 1 when last bit of 1-byte serial character is

transmitted.

Parity error

[Clearing conditions] • Reset or transition to standby mode

• Read PER when PER = 1, then write 0 in PER.

[Setting condition]

Parity error (parity of receive data does not match parity

setting of O/

E bit in SMR)

Framing error (for serial communication interface)

[Clearing conditions] • Reset or transition to standby mode

• Read FER when FER = 1, then write 0 in FER.

[Setting condition]

Framing error (stop bit is 0)

Error signal status (for smart card interface)

[Clearing conditions] • Reset or transition to standby mode

• Read ERS when ERS = 1, then write 0 in ERS.

[Setting condition]

A low error signal is received.

Overrun error

[Clearing conditions] • Reset or transition to standby mode

• Read ORER when ORER = 1, then write 0 in ORER.

[Setting condition]

Overrun error (reception of the next serial data ends when RDRF = 1)

Receive data register full

[Clearing conditions] • Reset or transition to standby mode

• Read RDRF when RDRF = 1, then write 0 in RDRF.

• The DMAC reads data from RDR.

[Setting condition]

Serial data is received normally and transferred from RSR to RDR.

Transmit data register empty

Note: 1. Only 0 can be written, to clear the flag.

[Clearing conditions] • Read TDRE when TDRE = 1, then write 0 in TDRE.

• The DMAC writes data in TDR.

[Setting conditions]

• Reset or transition to standby mode

• TE is 0 in SCR.

• Data is transferred from TDR to TSR, enabling new data to be written in TDR

Transmit end (for smart card interface)

[Clearing conditions]

• Read TDRE when TDRE = 1, then write 0 in TDRE.

• The DMAC writes data in TDR.

[Setting conditions]

• Reset or transition to standby mode

• TE is cleared to 0 in SCR and FER/ERS is cleared to 0.

• TDRE is 1 and FER/ERS is 0 (normal transmission) 2.5 etu*

(when GM = 0) or 1.0 etu (when GM = 1) after 1-byte serial

character is transmitted.

Note: * etu (Elementary time unit: the time for transfer of one bit)

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