H8SLASH3028F datasheet(120/923 Pages) RENESAS

120 / 923 page

Rev. 2.00, 09/03, page 90 of 890

Bit 1—Priority Level B1 (IPRB1): Selects the priority level of SCI channel 2 interrupt requests.

Bit 1

IPRB1

Description

SCI channel 2 interrupt requests have priority level 0 (low priority)

(Initial value)

SCI channel 2 interrupt requests have priority level 1 (high priority)

Bit 0—Reserved: This bit can be written and read, but it does not affect interrupt priority.

5.2.3

IRQ Status Register (ISR)

ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt

requests.

Bit

Initial value

Read/Write

—

These bits indicate IRQ to IRQ

interrupt request status

Note: * Only 0 can be written, to clear flags.

—

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

IRQ0F

R/(W)*

IRQ to IRQ flags

Reserved bits

ISR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Reserved: These bits can not be modified and are always read as 0.

Bits 5 to 0—IRQ5 to IRQ0 Flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ5 to

IRQ0 interrupt requests.

Bits 5 to 0

IRQ5F to IRQ0F Description

[Clearing conditions]

(Initial value)

0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.

IRQnSC = 0,

IRQn input is high, and interrupt exception handling is carried out.

IRQnSC = 1 and IRQn interrupt exception handling is carried out.

[Setting conditions]

IRQnSC = 0 and

IRQn input is low.

IRQnSC = 1 and

IRQn input changes from high to low.

Note: n = 5 to 0

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