H8SLASH3028F datasheet(199/923 Pages) RENESAS

199 / 923 page

Rev. 2.00, 09/03, page 169 of 890

• Figure 6.32 shows typical interconnections when using two 16-Mbit DRAMs using a × 8-bit

organization, and the corresponding address map. The DRAMs used in this example are of the

11-bit row address

× 10-bit column address type. The CS2 pin is used as the common RAS

output pin for areas 2 and 3. When the

DRAM address space spans a number of contiguous

areas, as in this example, the appropriate setting of bits DRAS2 to DRAS0 enables a single

pin to be used as the common

RAS output pin for a number of areas, and makes it possible to

directly connect large-capacity DRAM with address space that spans a maximum of four areas.

Any unused

CS pins (in this example, the CS

3 pin) can be used as input/output ports.

CS2 (RAS2)

RD (WE)

A21, A10-A1

D15-D8

D7-D0

A10-A0

D7-D0

PB4 (UCAS)

PB5 (LCAS)

RAS

CAS

A10-A0

D7-D0

RAS

CAS

No.1

No.2

DRAM

(No.1)

H'400000

H'5FFFFE

H'600000

H'7FFFFE

H'800000

H'9FFFFE

H'A00000

H'BFFFFE

DRAM

(No.2)

CS2(RAS2)

CS4

CS5

PB4

(UCAS)

PB5

(LCAS)

H8/3028 Group chip

2-CAS 16-Mbit DRAM

11-bit row address

× 10-bit column address

× 8-bit organization

(a) Interconnections (example)

(b) Address map

16-Mbyte mode

Area 2

Area 3

Area 4

Area 5

Normal

Figure 6.32 Interconnections and Address Map for 16-Mbit DRAMs with

×××× 8-Bit

Organization

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