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H8/3028F Datasheet(PDF) 206 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 206 Page - Renesas Technology Corp |
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206 / 923 page ![]() Rev. 2.00, 09/03, page 176 of 890 Contention between RTCOR Write and Compare Match: If a compare match occurs in the T3 state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited. See figure 6.41. M φ RTCOR Compare match signal T1 T2 T3 N N+1 N RTCNT Internal write signal Address bus RTCOR address RTCOR write data Inhibited Figure 6.41 Contention between RTCOR Write and Compare Match RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may cause RTCNT to increment, depending on the switchover timing. Table 6.10 shows the relation between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of RTCNT. The RTCNT input clock is generated from the internal clock source by detecting the falling edge of the internal clock. If a switchover is made from a high clock source to a low clock source, as in case No. 3 in table 6.10, the switchover will be regarded as a falling edge, an RTCNT clock pulse will be generated, and RTCNT will be incremented. |
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