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H8/3028F Datasheet(PDF) 225 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 225 Page - Renesas Technology Corp |
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225 / 923 page ![]() Rev. 2.00, 09/03, page 195 of 890 7.2.2 I/O Address Registers (IOAR) An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits are all 1 (H'FFFF). Bit Initial value Read/Write 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 0 R/W 2 R/W 1 R/W Source or destination address Undetermined An IOAR functions as a source or destination address register depending on how the DMAC is activated: as a destination address register if activation is by a receive-data-full interrupt from serial communication interface (SCI) channel 0 or by an A/D converter conversion-end interrupt, and as a source address register otherwise. The IOAR value is held fixed. It is not incremented or decremented when a transfer is executed. The IOARs are not initialized by a reset or in standby mode. 7.2.3 Execute Transfer Count Registers (ETCR) An execute transfer count register (ETCR) is a 16-bit readable/writable register that specifies the number of transfers to be executed. These registers function in one way in I/O mode and idle mode, and another way in repeat mode. • I/O mode and idle mode Bit Initial value Read/Write 14 R/W 12 R/W 10 R/W 8 R/W 6 R/W 0 R/W 4 R/W 2 R/W Transfer counter Undetermined 15 R/W 13 R/W 11 R/W 9 R/W 7 R/W 1 R/W 5 R/W 3 R/W In I/O mode and idle mode, ETCR functions as a 16-bit counter. The count is decremented by 1 each time one transfer is executed. The transfer ends when the count reaches H'0000. |
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