H8SLASH3028F datasheet(247/923 Pages) RENESAS

247 / 923 page

Rev. 2.00, 09/03, page 217 of 890

In repeat mode ETCRH is used as the transfer counter while ETCRL holds the initial transfer

count. ETCRH is decremented by 1 at each transfer until it reaches H'00, then is reloaded from

ETCRL. MAR is also restored to its initial value, which is calculated from the DTSZ and DTID

bits in DTCR. Specifically, MAR is restored as follows:

MAR

← MAR – (–1)DTID · 2DTSZ · ETCRL

ETCRH and ETCRL should be initially set to the same value.

In repeat mode transfers continue until the CPU clears the DTE bit to 0. After DTE is cleared to 0,

if the CPU sets DTE to 1 again, transfers resume from the state at which DTE was cleared. No

CPU interrupt is requested.

As in I/O mode, MAR and IOAR specify the source and destination addresses. MAR specifies a

24-bit source or destination address. IOAR specifies the lower 8 bits of a fixed address. The upper

16 bits are all 1s. IOAR is not incremented or decremented.

Figure 7.6 illustrates how repeat mode operates.

Address T

Address B

Transfer

1 byte or word is

transferred per request

Legend

L = initial setting of MAR

N = initial setting of ETCRH and ETCRL

Address T = L

Address B = L + (–1)

• (2

• N – 1)

DTID

DTSZ

IOAR

Figure 7.6 Operation in Repeat Mode

H8/3028F Datasheet(PDF) 247 Page - Renesas Technology Corp