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H8/3028F Datasheet(PDF) 259 Page - Renesas Technology Corp

Part # H8/3028F
Description  Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series
PDF  923 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3028F Datasheet(HTML) 259 Page - Renesas Technology Corp

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Rev. 2.00, 09/03, page 229 of 890
7.4.8
DMAC Bus Cycle
Figure 7.13 shows an example of the timing of the basic DMAC bus cycle. This example shows a
word-size transfer from a 16-bit two-state access area to an 8-bit three-state access area. When the
DMAC gets the bus from the CPU, after one dead cycle (Td), it reads from the source address and
writes to the destination address. During these read and write operations the bus is not released
even if there is another bus request. DMAC cycles comply with bus controller settings in the same
way as CPU cycles.
φ
RD
HWR
LWR
T1
T2
T1
T2
Td
T1
T2
T1
T2
T3
T1
T2
T3
T1
T2
T1
T2
CPU cycle
DMAC cycle (1 word transfer)
CPU cycle
Source
address
Destination address
Address
bus
Figure 7.13 DMA Transfer Bus Timing (Example)



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