H8SLASH3028F datasheet(298/923 Pages) RENESAS

298 / 923 page

Rev. 2.00, 09/03, page 268 of 890

8.7.2

Table 8.10 summarizes the registers of port 6.

Table 8.10 Port 6 Registers

Address*

Name

Abbreviation

R/W

Initial Value

H'EE005

Port 6 data direction register

P6DDR

H'80

H'FFFD5

Port 6 data register

P6DR

R/W

H'80

Note: * Lower 20 bits of the address in advanced mode.

Port 6 Data Direction Register (P6DDR): P6DDR is an 8-bit write-only register that can select

input or output for each pin in port 6.

Bit 7 is reserved. It is fixed at 1, and cannot be modified.

Bit

Initial value

Read/Write

—

P6 DDR

Port 6 data direction 6 to 0

These bits select input or output for port 6 pins

Reserved bit

Modes 1 to 5 (Expanded Modes): P67 functions as the clock output pin (φ) or an input port. P67

is the clock output pin (

φ) if the PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input

port if this bit is set to 1.

P66 to P63 function as bus control output pins (LWR, HWR, RD, and AS), regardless of the

settings of bits P66DDR to P63DDR.

P62 to P60 function as bus control input/output pins (BACK, BREQ, and WAIT) or input/output

ports. For the method of selecting the pin functions, see table 8.11.

When P62 to P60 function as input/output ports, the pin becomes an output port if the

corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.

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