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H8/3028F Datasheet(PDF) 318 Page - Renesas Technology Corp |
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H8/3028F Datasheet(HTML) 318 Page - Renesas Technology Corp |
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318 / 923 page  Rev. 2.00, 09/03, page 288 of 890 PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7. It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software standby mode it retains its previous setting. Therefore, if a transition is made to software standby mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the corresponding pin maintains its output state. Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output data for port A. When port A functions as an output port, the value of this register is output. When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read. Bit Initial value Read/Write 0 PA 0 R/W 0 1 PA 0 R/W 1 2 PA 0 R/W 2 3 PA 0 R/W 3 4 PA 0 R/W 4 5 PA 0 R/W 5 6 PA 0 R/W 6 7 PA 0 R/W 7 Port A data 7 to 0 These bits store data for port A pins PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. |
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