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TS68HC901 Datasheet(PDF) 22 Page - STMicroelectronics |
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TS68HC901 Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 42 page ![]() 7 TIMER C AND D CONTROL REGISTER 0 TCDCR (1Dh) 0* CC2 CC1 CC0 0* DC2 DC1 DC0 CLEARED on RESET 0* Unused bits, read as zero. CC2-CC0 DC2-DC0 These bits are decoded to determine the timer operation mode. CC2 DC2 CC1 DC1 CC0 DC0 Operation Mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Timer Stopped* Delay Mode, ÷ 4 Prescaler Delay Mode, ÷ 10 Prescaler Delay Mode, ÷ 16 Prescaler Delay Mode, ÷ 50 Prescaler Delay Mode, ÷ 64 Prescaler Delay Mode, ÷ 100 Prescaler Delay Mode, ÷ 200 Prescaler * Regardless of the operation mode, counting is inhibited when the timer is stopped. The contents of the timer’s main counter is not affected, although any residual count in the prescaler is lost. SET: End of write cycle which clears the bit CLEARED: MPUwrites a zero Figure 15 : ® TS68HC901 22/42 |
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