TS68HC901 datasheet(23/42 Pages) STMICROELECTRONICS

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put lines TA0 and TB0. These control registers are

shown in Figure 14.

UNIVERSAL SYNCHRONOUS / ASYN-

CHRONOUS RECEIVER-TRANSMITTER

The universal synchronous / asynchronous recei-

ver-transmitter (USART) is a single full-duplex serial

channel with a double-buffered receiver and trans-

mitter. There are separate receive and transmit

clocks and separate receive and transmit status and

data bytes. The receive and transmit sections are al-

so assigned separate interrupt channels. Each sec-

tion has both a normal condition interrupt channel

and an error condition interrupt channel. These

channels can be optionally disabled from interrup-

ting the processor and instead, DMA transfers can

be performed using the receiver ready and transmit-

ter ready external CMFP signals.

CHARACTER PROTOCOLS

The CMFP USART supports asynchronous and

with the aid of a polynomial generator checker

(PGC) supports byte synchronous character for-

mats. These formats are selected independently of

the divide-by-one and divide-by-16 clock modes.

When the divide-by-one clock mode is selected,

synchronization must be accomplished externally.

The receiver will sample the serial data on the rising

edge of the receiver clock. In the divide-by-16 clock

mode, the data is sampled at mid-bit time to in-

crease transient noise rejection.

Also, when the divide-by-16 clock mode is selected,

the USART resynchronization logic is enabled. This

logic increases the channel’s clock skew tolerance.

When a valid transition is detected, an internal coun-

ter is reset to state zero. Transition checking is then

inhibited until state four. Then at state eight, the pre-

vious state of the transition checking logic is clocked

into the receive shift register.

ASYNCHRONOUS FORMAT

Variable word length and start / stop bit configura-

tions are available under software control for asyn-

chronous operation. The word length can be five to

eight bits and one, one and one-half, or two stop bits

can be selected. The user can also select odd, even,

or no parity. For character lengths of less than eight

bits, the assembled character will consist of the re-

quired number of data bits followed by zeros in the

unused bit positions and a parity bit, if parity is en-

abled.

In the asynchronous format, start bit detection is al-

ways enabled. New data is not shifted into the re-

ceive shift register until a zero bit is received. When

the divide-by-16 clock mode is selected, the false

start bit logic is also active. Any transition must be

stable for three positive receive clock edges to be

considered valid. Then a valid zero-to-one transition

must not occur for at least eight additional positive

clock edges.

SYNCHRONOUS FORMAT

When the synchronous character format is selected,

the 8-bit synchronous character loaded into the syn-

chronous character register is compared to received

serial data until a match is found. Once synchroni-

zation is established, incoming data is clocked into

the receiver. The synchronous word will be conti-

nuously transmitted during an underrun condition.

All synchronous characters can be optionally strip-

ped from the receive buffer. Figure 15 shows the

synchronous character register.

The synchronous character is typically written after

the data word length is selected, since unused bits

in the synchronous character register are zeroed

out. When parity is enabled, synchronous word

length is the data word length plus one. The CMFP

will compute and append the parity bit for the syn-

chronous word when a word length of eight is selec-

ted. However, if the word length is less than eight,

USART DATA REGISTER

UDR

(2Fh)

SYNCHRONOUS CHARACTER REGISTER

SCR

(27h)

Figure 16 :

TS68HC901

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