P89LPC954 datasheet(35/69 Pages) NXP

35 / 69 page

P89LPC952_954_4

Product data sheet

Rev. 04 — 24 July 2008

35 of 69

NXP Semiconductors

P89LPC952/954

8-bit microcontroller with 10-bit ADC

stop bit is not saved. The baud rate is programmable to either 1

⁄

16 or

⁄

32 of the CPU clock

frequency, as determined by the SMOD1 bit in PCON. The SMOD1 bit controls the Timer

1 output rate available to both UARTs.

7.19.4 Mode 3

11 bits are transmitted (through TXDn) or received (through RXDn): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 7.19.5 “Baud rate generator and selection”).

7.19.5 Baud rate generator and selection

Each enhanced UART has an independent Baud Rate Generator. The baud rate is

determined by a baud-rate preprogrammed into the BRGR1_n and BRGR0_n SFRs

which together form a 16-bit baud rate divisor value that works in a similar manner as

Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be

used for other timing functions.

The UARTs can use either Timer 1 or their respective baud rate generator output (see

Figure 8). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared.

The independent Baud Rate Generators use OSCCLK.

7.19.6 Framing error

Framing error is reported in the status register (SnSTAT). In addition, if SMOD0 (PCON.6)

is ‘1’, framing errors can be made available in SnCON.7 respectively. If SMOD0 is ‘0’,

SnCON.7 is SM0_n. It is recommended that SM0_n and SM1_n (SnCON.7:6) are set up

when SMOD0 is ‘0’.

7.19.7 Break detect

Break detect is reported in the status register (SnSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

7.19.8 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be

written to SnBUF while the ﬁrst character is being transmitted. Double buffering allows

transmission of a string of characters with only one stop bit between any two characters,

as long as the next character is written between the start bit and the stop bit of the

previous character.

Fig 8.

Baud rate sources for UART (Modes 1, 3)

baud rate modes 1 and 3

SBRGS = 1

SBRGS = 0

SMOD1 = 0

SMOD1 = 1

timer 1 overflow

(PCLK-based)

baud rate generator

(CCLK-based)

002aaa897

÷2

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