| Electronic Components Datasheet Search |
|
P89LPC954 Datasheet(PDF) 12 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P89LPC954 Datasheet(HTML) 12 Page - NXP Semiconductors |
|
12 / 69 page ![]() P89LPC952_954_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 July 2008 12 of 69 NXP Semiconductors P89LPC952/954 8-bit microcontroller with 10-bit ADC P2.5/SPICLK 27 31 25 I/O P2.5 — Port 2 bit 5. I/O SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. P2.6 26 - - I/O P2.6 — Port 2 bit 6. P2.7 5 - - I/O P2.7 — Port 2 bit 7. P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port configurations” and Table 11 “Static characteristics” for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below: P3.0/XTAL2/ CLKOUT 7 12 6 I/O P3.0 — Port 3 bit 0. O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration. O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer. P3.1/XTAL1 6 11 5 I/O P3.1 — Port 3 bit 1. I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer. P4.0 to P4.7 I/O Port 4: Port 4 is an 8-bit I/O port with a user-configurable output type. During reset Port 4 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 4 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 7.13.1 “Port configurations” and Table 11 “Static characteristics” for details. All pins have Schmitt triggered inputs. Port 4 also provides various special functions as described below: P4.0 25 30 24 I/O P4.0 — Port 4 bit 0. P4.1/TRIG 24 29 23 I/O P4.1 — Port 4 bit 1. O TRIG — Debugger trigger output. P4.2/TXD1 23 28 22 I/O P4.2 — Port 4 bit 2. O TXD1 — Transmitter output for serial port 1. P4.3/RXD1 22 27 21 I/O P4.3 — Port 4 bit 3. I RXD1 — Receiver input for serial port 1. Table 3. Pin description …continued Symbol Pin Type Description LQFP48 PLCC44 LQFP44 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |