PCF8562TTSLASHS400SLASH2 datasheet(14/36 Pages) NXP

14 / 36 page

PCF8562_3

Product data sheet

Rev. 3 — 2 December 2008

14 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

7.10 Display RAM

The display RAM is a static 32

× 4-bit RAM which stores LCD data. A logic 1 in the RAM

bit-map indicates the on-state of the corresponding LCD segment; similarly, a logic 0

indicates the off-state. There is a one-to-one correspondence between the RAM

addresses and the segment outputs, and between the individual bits of a RAM word and

the backplane outputs. The display RAM bit map Figure 9 shows the rows 0 to 3 which

correspond with the backplane outputs BP0 to BP3, and the columns 0 to 31 which

correspond with the segment outputs S0 to S31. In multiplexed LCD applications the

segment data of the ﬁrst, second, third and fourth row of the display RAM are

time-multiplexed with BP0, BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8562, the display bytes received are stored in

the display RAM in accordance with the selected LCD drive mode. The data is stored as it

arrives and does not wait for an acknowledge cycle as with the commands. Depending on

the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets.

For example, in the 1:2 mode, the RAM data is stored every second bit. To illustrate the

ﬁlling order, an example of a 7-segment numeric display showing all drive modes is given

in Figure 10; the RAM ﬁlling organization depicted applies equally to other LCD types.

With reference to Figure 10, in the static drive mode, the eight transmitted data bits are

placed in row 0 of eight successive display RAM addresses.

In the 1:2 mode, the eight transmitted data bits are placed in row 0 and 1 of four

successive display RAM addresses.

In the 1:3 mode, these bits are placed in row 0, 1 and 2 to three successive addresses,

display RAM words, with bit 2 of the third address left unchanged. This last bit may, if

necessary, be controlled by an additional transfer to this address but care should be taken

to avoid overwriting adjacent data because always full bytes are transmitted; otherwise

this segment should not be connected to the module.

In the 1:4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two

successive display RAM addresses.

Display RAM bit map showing direct relationship between RAM addresses and segment outputs;

also between bits in a RAM word and the backplane outputs.

Fig 9.

Display RAM bit map

1234

display RAM addresses (rows) / segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

001aac265

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