PCF8562TTSLASHS400SLASH2 datasheet(22/36 Pages) NXP

22 / 36 page

PCF8562_3

Product data sheet

Rev. 3 — 2 December 2008

22 of 36

NXP Semiconductors

PCF8562

Universal LCD driver for low multiplex rates

An acknowledgement after each byte is asserted only by the PCF8562s that are

addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master

asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus

access.

7.17 Command decoder

The command decoder identiﬁes command bytes that arrive on the I2C-bus.

The commands available to the PCF8562 are deﬁned in Table 7.

[1]

Not used.

All available commands carry a continuation bit C in their most signiﬁcant bit position as

shown in Figure 16. When this bit is set, it indicates that the next byte of the transfer to

arrive will also represent a command. If this bit is reset, it indicates that the command byte

is the last in the transfer. Further bytes will be regarded as display data (see Table 8).

Table 7.

Deﬁnition of PCF8562 commands

Command

Operation Code

Reference

Bit

mode-set

[1]

Table 9

load-data-pointer

Table 10

device-select

1100A2

Table 11

bank-select

11110I

Table 12

blink-select

1110A

BF1

BF0

Table 13

Table 8.

C bit description

Bit

Symbol

Value

Description

continue bit

last control byte in the transfer; next byte will be regarded

as display data

control bytes continue; next byte will be a command too

PCF8562TT/S400/2 Datasheet(PDF) 22 Page - NXP Semiconductors

PCF8562TT/S400/2 Datasheet(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL