CS42888-CQZ datasheet(44/61 Pages) CIRRUS

44 / 61 page

DS717F2

CS42888

6.5.4

ADC Digital Interface Format (ADC_DIF[2:0])

Default = 110

Function:

These bits select the digital interface format used for the ADC serial port. The required relationship between

the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options

are detailed in the section “CODEC Digital Interface Formats” on page 30. Refer to Table 9, “Serial Audio

Interface Channel Allocations,” on page 33.

Note:

The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format.

6.6

ADC Control & DAC De-Emphasis (Address 05h)

6.6.1

ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)

Default = 0

Function:

When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset

value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter

Characteristics” on page 13.

Right Justified, 16-bit data

Figure 16

One-Line #1, 20-bit

Figure 17

One-Line #2, 24-bit

Figure 18

TDM Mode, 24-bit (slave only)

Figure 19

Reserved

ADC_DIF2

ADC_DIF1

ADC_DIF0

Description

Format

Figure

Left Justified, up to 24-bit data

Figure 15

I²S, up to 24-bit data

Figure 14

Right Justified, 24-bit data

Figure 16

Right Justified, 16-bit data

Figure 16

One-Line #1, 20-bit

Figure 17

One-Line #2, 24-bit

Figure 18

TDM Mode, 24-bit (slave only)

Figure 19

Reserved

Table 13. ADC Digital Interface Formats

543

ADC1-2_HPF

FREEZE

Reserved

DAC_DEM

ADC1

SINGLE

ADC2

SINGLE

Reserved

DAC_DIF2

DAC_DIF1

DAC_DIF0

Description

Format

Figure

Table 12. DAC Digital Interface Formats

CS42888-CQZ Datasheet(PDF) 44 Page - Cirrus Logic

CS42888-CQZ Datasheet(HTML) 44 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL