A40MX02-PL100M datasheet(29/123 Pages) ACTEL

29 / 123 page

40MX and 42MX FPGA Families

v6.0

1-23

Timing Models

Note:

* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.

Figure 1-17 • 40MX Timing Model*

Notes: *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.

† Input module predicted routing delay.

Figure 1-18 • 42MX Timing Model*

Output Delay

Input Delay

Logic Module

Internal Delays

tDLH=3.32 ns

tENHZ=7.92 ns

tRD1=1.28 ns

tRD2=1.80 ns

tRD4=2.33 ns

tRD8=4.93 ns

I/O Module

tPD=1.24 ns

tCO=1.24 ns

tIRD1=2.09 ns

tIRD4=3.64 ns

tIRD8=5.73 ns

tINYL=0.62 ns t

IRD2=2.59 ns

I/O Module

FMAX=180 MHz

tCKH=4.55 ns

FO=128

Array

Clock

Predicted

Routing

Delays

Array

Clocks

Combin

-atoria l

Logic

include

FO = 32

Output Delays

Internal Delays

Input Delays

I/O Module

†

Combinatorial

Logic Module

Sequential

Logic Module

I/O Module

Predicted

Routing

Delays

RD1=0.7 ns

RD2=1.9 ns

RD4=1.4 ns

RD8=2.3 ns

OUTH=0.00 ns

OUTSU=0.3 ns

GLH=2.6 ns

DLH=2.5 ns

ENHZ=4.9 ns

RD1=0.70 ns

LCO=5.2 ns (light loads, pad-to-pad)

CO=1.3 ns

SUD=0.3 ns

HD=0.00 ns

PD=1.2 ns

IRD1=2.0 ns

INYL=0.8 ns

INH=0.0 ns

INSU=0.3 ns

INGL=1.3 ns

MAX=296 MHz

CKH=2.70 ns

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