TMS320F241FN datasheet(7/116 Pages) TI

7 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’F243 PGE Package

NAME

144

QFP

TYPE†

RESET

STATE‡

DESCRIPTION

NO.

STATE‡

ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS

ADCIN00

ADCIN01

ADCIN02

ADCIN03

Analog inputs to the ADC

ADCIN04

Analog inputs to the ADC

ADCIN05

144

ADCIN06

143

ADCIN07

139

VCCA

137

–

Analog supply voltage for ADC (5 V). VCCA must be isolated from

digital supply voltage.

VSSA

135

–

Analog ground reference for ADC

VREFHI

141

–

ADC analog high-voltage reference input

VREFLO

142

–

ADC analog low-voltage reference input

EVENT MANAGER

T1PWM/T1CMP/

IOPB4

130

I/O/Z

Timer 1 compare output/general-purpose bidirectional digital I/O

(GPIO).

T2PWM/T2CMP/

IOPB5

128

I/O/Z

Timer 2 compare output/GPIO

TDIR/

IOPB6

I/O

Counting direction for general-purpose (GP) timer/GPIO. If TDIR=1,

upward counting is selected. If TDIR=0, downward counting is

selected.

TCLKIN/

IOPB7

I/O

External clock input for GP timer/GPIO. Note that timer can also use

the internal device clock.

CAP1/QEP0/

IOPA3

123

I/O

Capture input #1/quadrature encoder pulse input #0/GPIO

CAP2/QEP1/

IOPA4

121

I/O

Capture input #2/quadrature encoder pulse input #1/GPIO

CAP3/

IOPA5

119

I/O

Capture input #3/GPIO

PWM1/

IOPA6

102

I/O/Z

Compare/PWM output pin #1 or GPIO

PWM2/

IOPA7

100

I/O/Z

Compare/PWM output pin #2 or GPIO

PWM3/

IOPB0

I/O/Z

Compare/PWM output pin #3 or GPIO

PWM4/

IOPB1

I/O/Z

Compare/PWM output pin #4 or GPIO

PWM5/

IOPB2

I/O/Z

Compare/PWM output pin #5 or GPIO

PWM6/

IOPB3

I/O/Z

Compare/PWM output pin #6 or GPIO

PDPINT§

Power drive protection interrupt input. This interrupt, when activated,

puts the PWM output pins in the high-impedance state should motor

drive/power converter abnormalities, such as overvoltage or

overcurrent, etc., arise. PDPINT is a falling-edge-sensitive interrupt.

After the falling edge, this pin must be held low for two clock cycles

for the core to recognize the interrupt.

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.

¶ Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS

is enabled.

NOTE:

Bold, italicized pin names indicate pin function after reset.

TMS320F241FN Datasheet(PDF) 7 Page - Texas Instruments

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