TMS320VC5504 datasheet(68/128 Pages) TI

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6.5 Clock PLLs

6.5.1

PLL Device-Specific Information

6.5.2

Clock PLL Considerations With External Clock Sources

TMS320VC5504

Fixed-Point Digital Signal Processor

SPRS609A – JUNE 2009 – REVISED JULY 2009

www.ti.com

The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective

series resistance (ESR) specified in Table 6-2. The load capacitors, C1 and C2 are the total capacitance

of the circuit board and components, excluding the IC and crystal. The load capacitor value is usually

approximately twice the value of the crystal's load capacitance, CL, which is specified in the crystal

manufacturer's datasheet and should be chosen such that the equation below is satisfied. All discrete

components used to implement the oscillator circuit should be placed as close as possible to the

associated oscillator pins (USB_MXI and USB_MXO) and to the USB_VSSOSC pin.

Table 6-2. Input Requirements for Crystal on the 12-MHz USB Oscillator

PARAMETER

MIN

NOM

MAX

UNIT

Start-up time (from power up until oscillating at stable frequency of

0.100

12 MHz)(1)

Oscillation frequency

MHz

ESR

100

Ω

(2)Frequency stability

±100

ppm

Maximum shunt capacitance

Maximum crystal drive

330

µW

(1)

The startup time is highly dependent on the ESR and the capacitive load of the crystal.

(2)

If the USB is used, a 12-MHz,

±100-ppm crystal is recommended.

The VC5504 DSP uses a software-programmable PLL to generate frequencies required by the CPU,

DMA, and peripherals. The reference clock for the PLL is taken from either the CLKIN pin or the RTC

on-chip oscillator (as specified through the CLK_SEL pin). The PLL is controlled through the system clock

generator which is discussed in further detail in the TMS320VC5505 DSP System User's Guide (literature

number SPRUFP0).

There is a minimum and maximum operating frequency for CLKIN, PLLOUT, and the system clock

(SYSCLK). The system clock generator must be configured not to exceed any of these constraints

documented in this section (certain combinations of external clock inputs, internal dividers, and PLL

multiply ratios might not be supported). For these constraints see and the Clock Generator (Figure 4) of

the TMS320VC5505 DSP System User's Guide (literature number SPRUFP0).

The PLL has a lock time requirements that must be followed. The PLL lock time is the amount of time

needed for the PLL to complete its phase-locking sequence.

For details on the PLL initialization software sequence, see the TMS320VC5505 DSP System User's

Guide (literature number SPRUFP0).

If the CLKIN pin is used to provide the reference clock to the PLL, to minimize the clock jitter a single

clean power supply should power both the VC5504 device and the external clock oscillator circuit. The

minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements, see

Section 6.5.3, Clock PLL Electrical Data/Timing (Input and Output Clocks).

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock

source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Temperature, and Section 6.5.3, Clock

PLL Electrical Data/Timing (Input and Output Clocks).

Peripheral Information and Electrical Specifications

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