TMS320VC5504 datasheet(24/128 Pages) TI

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TMS320VC5504

Fixed-Point Digital Signal Processor

SPRS609A – JUNE 2009 – REVISED JULY 2009

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Table 3-7. RESET, Interrupts, and JTAG Terminal Functions (continued)

SIGNAL

TYPE(1)

OTHER(2)(3)

DESCRIPTION

NAME

NO.

IEEE standard 1149.1 test clock. TCK is normally a free-running clock

signal with a 50% duty cycle. The changes on test access port (TAP) of

input signals TMS and TDI are clocked into the TAP controller,

instruction register, or selected test data register on the rising edge of

TCK. Changes at the TAP output signal (TDO) occur on the falling

IPU

edge of TCK.

TCK

DVDDIO

If the emulation header is located greater than 6 inches from the

device, TCK must be buffered.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

IEEE standard 1149.1 reset signal for test and emulation logic. TRST,

when high, gives the IEEE standard 1149.1 scan system control of the

operations of the device. If TRST is not connected or driven low, the

device operates in its functional mode, and the IEEE standard 1149.1

signals are ignored. The VC5504 will not operate properly if this reset

IPD

TRST

pin is never asserted low.

DVDDIO

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

It is recommended that an external pulldown resistor be used in

addition to the IPD -- especially if there is a long trace to an emulation

header.

Emulator 1 pin. EMU1 is used as an interrupt to or from the emulator

system and is defined as input/output by way of the emulation logic.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

IPU

An external pullup to DVDDIO is required to provide a signal rise time of

EMU1

I/O/Z

DVDDIO

less than 10

µsec. A 4.7-kΩ resistor is suggested for most applications.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

Emulator 0 pin. When TRST is driven low and then high, the state of

the EMU0 pin is latched and used to connect the JTAG pins (TCK,

TMS, TDI, TDO) to either the IEEE1149.1 Boundary-Scan TAP (when

the latched value of EMU0 = 0) or to the DSP Emulation TAP (when the

latched value of EMU0 = 1). Once TRST is high, EMU0 is used as an

interrupt to or from the emulator system and is defined as input/output

IPU

EMU0

I/O/Z

by way of the emulation logic.

DVDDIO

An external pullup to DVDDIO is required to provide a signal rise time of

less than 10

µsec. A 4.7-kΩ resistor is suggested for most applications.

For board design guidelines related to the emulation header, see the

XDS560 Emulator Technical Reference (literature number: SPRU589).

The IPU resistor on this pin can be enabled or disabled via the

PDINHIBR2 register.

EXTERNAL INTERRRUPTS

IPU

External interrupt inputs (INT1 and INT0). These pins are maskable via

INT1

DVDDIO

their specific Interrupt Mask Register (IMR1, IMR0) and the interrupt

mode bit. The pins can be polled and reset by their specific Interrupt

Flag Register (IFR1, IFR0).

IPU

INT0

The IPU resistor on these pins can be enabled or disabled via the

DVDDIO

PDINHIBR2 register.

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