CY8CLED04D01, CY8CLED04D02
CY8CLED04G01, CY8CLED03D01
CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *G
Page 21 of 52
12.3 CY8CLED04DOCD1 56-Pin Part Pinout (with OCD)
The CY8CLED04DOCD1 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and
“FN0”) is capable of Digital I/O.
Table 12-3. CY8CLED04DOCD1 56-Pin Part Pinout (QFN)
Pin
No.
Type
Name
Description
Figure 12-3. CY8CLED04DOCD1 56-Pin PowerPSoC Device
Digital
Rows
Analog
Columns
Power
Peripherals
1
I/O
I
P1[0]
GPIO/I2C SDATA (secondary) ISSP
primary
2
I/O
I
P2[2]
GPIO/Direct Switch Cap connection
3
I/O
I/O
P0[3]
GPIO/Ainput (coIO) Aoutput (coIO)
4
I/O
I/O
P0[5]
GPIO/Ainput (coIO) Aoutput (coIO) /
Capsense Ref Cap
5
I/O
I
P0[7]
GPIO, connects to Analog Column
Capsense Ref Cap
6
I/O
I
P1[1]
GPIO/I2C SCLK (secondary) ISSP
primary
7
I/O
I
P1[5]
GPIO/I2C SDATA (Primary)
8
I/O
I
P1[7]
GPIO/ I2C SCLK (Primary)
9
VSS
Digital Ground
10
I/O
OCDE
On Chip Debugger Port
11
I/O
OCDO
On Chip Debugger Port
12
I/O
CCLK
On Chip Debugger Port
13
I/O
HCLK
On Chip Debugger Port
14
I
XRES
External Reset
15
VDD
Digital Power Supply
16
VSS
Digital Ground
17
AVSS
Analog Ground
18
AVDD
Analog Power Supply
19
I
CSN2
Current Sense Negative Input 2
20
CSP2
Current Sense Positive Input and
Power Supply - CSA2
21
CSP3
Current Sense Positive Input and
Power Supply - CSA3
22
I
CSN3
Current Sense Negative Input 3
23
SREGCOMP Voltage Regulator Error Amp Comp
24
I
SREGFB
Regulator Voltage Mode Feedback
Node
25
I
SREGCSN
Current Mode Feedback Negative
26
I
SREGCSP
Current Mode Feedback Positive
27
O
SREGSW
Switch Mode Regulator OUT
28
SREGHVIN
Switch Mode Regulator IN
29
GDVDD
Gate Driver Power Supply
Pin
No.
Type
Name
Description
30
GDVSS
Gate Driver Ground
Digital
Rows
Analog
Columns
Power
Peripherals
31
PGND3
Power FET Ground 3
44
GDVDD Gate Driver Power Supply
32
O
GD3
External Low Side Gate Driver 3
45
I/O
FN0[0]
Function I/O
33
SW3
Power Switch 3
46
I/O
FN0[1]
Function I/O
34
PGND2
Power FET Ground 2
47
I/O
FN0[2]
Function I/O
35
O
GD2
External Low Side Gate Driver 2
48
I/O
FN0[3]
Function I/O
36
SW2
Power Switch 2
49
I
CSN0
Current Sense Negative Input 0
37
SW1
Power Switch 1
50
CSP0
Current Sense Positive Input and
Power Supply - CSA0
38
O
GD1
External Low Side Gate Driver 1
51
CSP1
Current Sense Positive Input and
Power Supply - CSA1
39
PGND1
Power FET Ground 1
52
I
CSN1
Current Sense Negative Input 1
40
SW0
Power Switch 0
53
I/O
I
P0[4]
GPIO/Connects to Analog Column
(1), bandgap output
41
O
GD0
External Low Side Gate Driver 0
54
VDD
Digital Power Supply
42
PGND0
Power FET Ground 0
55
VSS
Digital Ground
43
GDVSS
Gate Driver Ground
56
I/O
I
P1[4]
GPIO / External Clock Input
QFN Top View
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
OCDE
OCDO
CCLK
HCLK
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PGND0
GD0
SW0
PGND1
GD1
SW1
SW2
GD2
PGND2
SW3
GD3
PGND3
GDVSS
GDVDD
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Exposed
Pad
* Connect Exposed Pad to PGNDx
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