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CY8CLED04D01, CY8CLED04D02
CY8CLED04G01, CY8CLED03D01
CY8CLED03D02, CY8CLED03G01
CY8CLED02D01, CY8CLED01D01
Document Number: 001-46319 Rev. *G
Page 3 of 52
Figure 2-2. CY8CLED04G01 Logic Block Diagram
4 Channel PWM/
PrISM/DMM
From Analog Mux
Auxiliary
Power
Regulator
DAC0
CSP0
GD 0
Hysteretic Mode
Controller 0
CSN0
DAC1
CSA0
DAC2
CSP1
GD 1
Hysteretic Mode
Controller 1
CSN1
DAC3
CSA1
DAC4
CSP2
GD 2
Hysteretic Mode
Controller 2
CSN2
DAC5
CSA2
DAC6
CSP3
Hysteretic Mode
Controller 3
CSN3
DAC7
FN0{0,1,2,3}
CSA3
6
SREGSW
SREGHVIN
External
Gate Drive 0
External
Gate Drive 1
External
Gate Drive 2
External
Gate Drive 3
Digital Mux
Analog Mux
DIGITAL SYSTEM
SRAM
1K
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
CPU Core (M8C)
SROM
Flash 16K
Digital
Block
Array
Digital
Clocks
SYSTEM RESOURCES
ANALOG SYSTEM
Analog Ref.
Analog
Block Array
Internal
Voltage Ref.
POR and LVD
System Resets
2 MACs
Decimator Type
2
I2C
Analog
Input Muxing
4
4
PORT2{2}
PORT0{3,4,5,7}
PORT1{0,1,4,5,7}
AINX
SREGCSN
SREGCSP
SREGFB
SREGCOMP
GD 3
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