LTC6412CUFPBF datasheet(17/24 Pages) LINER

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LTC6412

6412f

Signal Compression Characteristics

The graph entitled, Input and Output P1dB, illustrates

an important characteristic of the LTC6412 VGA. At gain

settings above –5dB, the output ampliﬁer limits the linear

power handling capability, but at gain settings below

–5dB, the input attenuator ladder limits the linear power

handling capability. The linear input power limitations at

minimum gain do not affect the overall performance of

a signal chain if the preceding mixer or ampliﬁer stage

exhibits an OP1dB < 19dBm and an OIP3 < 50dBm.

Test Circuits

The fully-differential nature of the LTC6412 design requires

two test circuits to generate the performance information

presented in this data sheet.

Test Circuit A is DC1464A, a 2-port demonstration circuit

with input/output balun transformers to allow for direct

connection to a 2-port network analyzer or other single-

ended 50Ω test system. The balun transformers limit the

high and low frequency performance of the LTC6412 but

allow for simple and reasonably accurate measurements

from 70MHz to 380MHz. The gain control signal is supplied

to either of the VG turrets for DC control measurements

or through the VGAIN SMA connector for transient control

signal measurements. Clip leads to the gain control turrets

are susceptible to noise pickup and should be lowpass

ﬁltered to avoid AM upconversion artifacts. While using

the ±VG turrets, a 4.7μF capacitor from the VGAIN SMA

input to ground provides an effective lowpass ﬁlter.

Typical data curves quoted for Test Circuit A are measured

at the plane of the SMA connectors and are NOT corrected

for any losses introduced by the input and output baluns,

estimated at approximately 0.5dB and 1.2dB, respectively.

All typical AC data reported in this data sheet correspond

to Test Circuit A, except for mixed-mode S-parameters of

the form Sdd21, Scc21, etc.

APPLICATIONS INFORMATION

Test Circuit B uses a 4-port network analyzer to measure

differential mode and common mode S-parameters

beyond the frequency limitations imposed by the balun

transformers and associated circuitry. A matching calibra-

tion set establishes the measurement reference planes

shown in Test Circuit B. The output plane is deﬁned at

the edge of the package while the input plane is deﬁned

at the edge of the input pair of 0402 capacitors. The IC

land and ground via pattern are identical to that shown

for Test Circuit A. The ground via pattern directly beneath

the package is critical to provide the proper RF ground to

produce the RF characteristics quoted in this data sheet.

All mixed-mode S-parameter typical data curves of the

form SxyAB correspond to Test Circuit B following the

deﬁnitions described in Figures 5 and 6.

Typical Application Circuits

Grounding and supply decoupling should closely follow the

suggested layout shown for Test Circuit A, but the input

and output networks can be customized to suit various

application requirements.

On the input side, the differential port impedance is very

close to 50Ω over all gain settings and application frequen-

cies. In a differential signal chain, the differential input signal

is easily supplied from a preceding differential output stage

with a suitable DC blocking capacitor of approximately

10nF. If the system employs a single-ended input signal

to the VGA, then a suitable balun is required to convert

to a differential input signal. The passive conversion from

50Ω single-ended to 50Ω differential is most effectively

accomplished with a 1:1 transmission-line balun such as

the ETC1-1-13 or MABA-007159. These 1:1 balun devices

are relatively inexpensive and offer excellent electrical

characteristics such as low loss, broad band response

and good phase matching.

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