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SPT7852

Figure 2 – Timing Diagram 1

Clock

Reset

Data

Valid (DAV)

Data

Output

(Channel A)

Data

Output

(Channel B)

1

2

3

4

Invalid

Invalid

Invalid

Invalid

Invalid

Invalid

Notes:

1)

Data Valid is forced low on Reset = High.

2)

Data updated on first rising edge of clock after Reset goes low.

3)

Data Valid rising edge will occur on the second rising edge of Clock

after Reset goes low. Use the rising edge of Data Valid to latch the ADC output data.

4)

Analog Input Data is sampled during the first clock cycle after Reset goes low.

Valid data output from this sample will be available 12 clock cycles

later (6 Data Valid cycles). All data during the 12 clock cycle latency is invalid.

CLOCK INPUT

The SPT7852 is driven from a single-ended TTL-input

clock. Because the pipelined architecture operates on the

rising edge of the clock input, the device can operate over a

wide range of input clock duty cycles without degrading the

dynamic performance. The device's sample rate is 1/2 of

the input clock frequency. (See timing diagram.)

TIMING AND RESET FUNCTION

The two on-board ADCs in the SPT7852 are driven off of a

single external TTL clock. This external clock must be 2X

the desired sample rate. In applications that require a

known phase relationship between the clock, analog input

sampling and valid data output, a reset function is provided

to establish a known phase relationship. (Because of the 2X

clock, an exact phase relationship will not be known other-

wise.) Refer to figure 2, Timing Diagram 1.

The reset pin is low for normal device operation. When reset

is brought high, Data Valid (DAV) is immediately forced low

and data output updates are suspended. Operation will re-

sume on the first rising edge of the clock after the reset pin

has been brought low. The first Data Valid rising edge will

occur on the second edge of the clock after the reset goes

low.

The first analog input sample will be taken during the first

clock cycle after reset goes low. Valid data from this

sample will be available 12 clock cycles later. All data dur-

ing this 12 cycle latency will be invalid (Refer to figure 3,

Timing Diagram 2.)