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SPT7852

1. Place the ferrite bead (*) as close to the ADC as possible.

2. Place 0.1

µF decoupling capacitors as close to the ADC as possible.

3. All capacitors are 0.1

µF surface-mount unless otherwise specified.

4. All analog input pins (references, analog input, clock input) must

be protected. (See absolute maximum ratings.)

11

Clock

Ref In

(+4 V)

CLK

.1

µF

.1

µF

4.7

µF

4.7

µF

+A5

Interfacing

Logic

11

3.3 V/5 V

FB

*

+A5

MSBINV

Reset

Digital

Output A

Digital

Output B

DAV

SPT7852

GND

+A5

EN

EN

3-st

FB

*

Figure 1 –Typical Interface Circuit

TYPICAL INTERFACE CIRCUIT

Very few external components are required to achieve the

stated device performance. Figure 1 shows the typical inter-

face requirements when using the SPT7852 in normal

circuit operation. The following sections provide descrip-

tions of the major functions and outline critical performance

criteria to consider for achieving the optimal device perfor-

mance.

POWER SUPPLIES AND GROUNDING

ply voltages on the SPT7852 be derived from a single ana-

log supply as shown in figure 1. A separate digital supply

using this power supply configuration to prevent a possible

latch-up condition on powerup.

CADEKA suggests that both the digital and the analog sup-

must be used for all interface circuitry. CADEKA suggests