AD9551

Rev. B | Page 29 of 40

REGISTER MAP

A bit that is labeled “aclr” is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to

a Logic 0 state upon completion of the indicated task.

Table 22. Register Map

Addr.

(Hex)

Register

Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

0x00

Serial port

control

0

LSB first

Soft reset

(aclr)

1

1

Device reset

LSB first

0

0x18

0x04

Readback

control

Unused

Unused

Unused

Unused

Unused

Unused

Unused

Readback

control

0x00

0x05

I/O update

Unused

Unused

Unused

Unused

Unused

Unused

Unused

I/O update

(aclr)

0x00

0x0A

Output PLL

PFD and

charge

pump

Output PLL PDF and charge pump current control[7:0]

(3.5 μA granularity, ~900 μA full scale)

0x80

0x0B

Output PLL

PFD and

charge

pump

Enable SPI

control of

charge

pump

current

Enable SPI

control of

antiback-

lash

period

CP mode[1:0]

Enable CP

mode

control

PFD

feedback

input edge

control

PFD

reference

input edge

control

Force VCO

to midpoint

frequency

0x30

0x0C

Output PLL

PFD and

charge

pump

Unused

CP offset

current

polarity

CP offset current[1:0]

Enable CP

offset

current

control

Reserved/

enable PFD

up divide-

by-2

Reserved/

enable PFD

down divide-

by-2

Reserved/

enable

feedback

divide-by-2

0x00

0x0D

Output PLL

PFD and

charge

pump

Antibacklash

control[1:0]

Unused

Unused

Unused

Unused

Unused

Output PLL

lock

detector

power-

down

0x00

0x0E

VCO

control

Calibrate

VCO (aclr)

Enable

automatic

level

control

Automatic level control threshold[2:0]

Enable SPI

control of

VCO

calibration

Boost VCO

supply

Enable SPI

control of

VCO band

setting

0x70

0x0F

VCO

control

VCO level control[5:0]

Unused

Unused

0x80

0x10

VCO

control

VCO band control[6:0]

Unused

0x80

0x11

Output PLL

control

N[7:0] (output SDM integer part)

0x00

0x12

Output PLL

control

MOD[19:12] (output SDM modulus)

0x80

0x13

Output PLL

control

MOD[11:4] (output SDM modulus)

0x00

0x14

Output PLL

control

MOD[3:0] (output SDM modulus)

Enable SPI

control of

output

frequency

Bypass

output SDM

Disable

output SDM

Reset

output PLL

0x00

0x15

Output PLL

control

FRAC[19:12] (output SDM fractional part)

0x20

0x16

Output PLL

control

FRAC[11:4] (output SDM fractional part)

0x00

0x17

Output PLL

control

FRAC[3:0] (output SDM fractional part)

Enable

OUTPUT

PLL LOCKED

pin as test

port

Test mux control[1:0]

0x01

0x18

Output PLL

control

P0 divider[2:0]

0x00