AD9551SLASHPCBZ datasheet(21/40 Pages) AD

21 / 40 page

AD9551

Rev. B | Page 21 of 40

HOLDOVER MODE

In the absence of both input references, the device enters holdover

mode. Holdover is a secondary function that is provided by the

input PLL. Because the DCXO has an external crystal as its fre-

quency source, it continues to operate in the absence of the input

reference signals. When the device switches to holdover, the DCXO

is held at the frequency at which it was operating just prior to

switchover. The device continues operating in this mode until

a reference signal becomes available; the device then exits holdover

mode, and the input PLL resynchronizes with the active reference.

JITTER TOLERANCE

Jitter tolerance is the ability of the AD9551 to maintain lock in the

presence of sinusoidal jitter. The AD9551 meets the DS1 reference

input jitter tolerance mask per Telcordia GR-1244-CORE (see

Figure 22). The acceptable jitter tolerance is the region above the

mask.

0.1

100

10k

100k

JITTER FREQUENCY (Hz)

EXTERNAL TIMING MASK

LINE TIMING MASK

Figure 22. Jitter Tolerance

EXTERNAL LOOP FILTER CAPACITOR

The output PLL loop filter requires the connection of an external

capacitor from LF (Pin 17) to LDO_VCO (Pin 22). The value of

the external capacitor depends on the operating mode (normal

or 19.44 MHz). Normal mode requires a 12 nF capacitor that sets

the loop bandwidth at approximately 70 kHz and ensures loop

stability over the intended operating parameters of the device.

The 19.44 MHz mode requires a 100 nF capacitor, along with

a change in the output PLL charge pump current to 25 μA, via

stability criteria as found in normal mode.

Note that the 19.44 MHz mode does not function properly

unless the user changes the output PLL charge pump current

from its default setting to 25 μA.

OUTPUT/INPUT FREQUENCY RELATIONSHIP

Following are the three equations that define the frequency

at OUT1 and OUT2 (fOUT1 and fOUT2, respectively). Note that

in the equations throughout this datasheet, the subscripted x

indicates A or B.

⎟

⎠

⎞

⎜

⎝

⎛

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

)

(

REF

MOD

FRAC

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ +

MOD

FRAC

OUT1

OUT2

where:

fREFA and fREFB are the input reference frequency, with the

subscripted A or B indicating REFA or REFB, respectively.

fIF is the frequency at the input of the output PLL’s PDF.

P0 and P1 are OUT1 divider values.

P2 is the OUT2 divider value.

K is the input mode scale factor.

NA, NB, FRACA, FRACB, MODA, and MODB are the input reference

divider values, with the A or B subscript indicating REFA or REFB,

respectively.

N, FRAC, and MOD are the feedback divider values for the

output PLL.

The various dividers have the following constraints:

{

}

∈

with SDM disabled

{

}

∈

with SDM active

{

}

∈ −

287

524

287

524

288

524

−

FRAC

{

}

∈

MOD

287

524

{

}

255

∈

{

}

∈

FRAC

575

048

{

}

575

048

MOD

∈

{

}

∈

{

}

∈

{

}

∈

The VCO imposes the following constraint on fIF:

MHz

4050

MHz

3350

⎟

⎠

⎞

⎜

⎝

⎛

≤

⎟

⎠

⎞

⎜

⎝

⎛

MOD

FRAC

MOD

FRAC

The input frequencies (fREFA and fREFB) must satisfy the following

relationship:

⎟⎟

⎠

⎞

⎛

⎞

⎛

)

(

REF

MOD

FRAC

⎜⎜

⎝

⎟⎟

⎠

⎜⎜

⎝

)

(

MOD

AD9551/PCBZ Datasheet(PDF) 21 Page - Analog Devices

AD9551/PCBZ Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL