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STM32F101XC Datasheet(PDF) 57 Page - STMicroelectronics

Part # STM32F101XC
Description  High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces
PDF  106 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101XC Datasheet(HTML) 57 Page - STMicroelectronics

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STM32F101xC, STM32F101xD, STM32F101xE
Electrical characteristics
Doc ID 14610 Rev 7
57/106
Figure 22.
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
1.
Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
Table 31.
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2)
1.
CL = 15 pF.
2.
Based on characterization, not tested in production.
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
5THCLK – 1.5
5THCLK + 2
ns
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
0.5
1.5
ns
tw(NOE)
FSMC_NOE low time
5THCLK – 1.5
5THCLK + 1.5
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time –1.5
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
7
ns
th(A_NOE)
Address hold time after FSMC_NOE high
0.1
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
0
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
0
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
2THCLK + 25
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
2THCLK + 25
ns
th(Data_NOE) Data hold time after FSMC_NOE high
0
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
5
ns
tw(NADV)
FSMC_NADV low time
THCLK + 1.5
ns
NBL
Data
FSMC_NEx
FSMC_NBL[1:0]
FSMC_D[15:0]
tv(BL_NE)
th(Data_NWE)
FSMC_NOE
Address
FSMC_A[25:0]
tv(A_NE)
tw(NWE)
FSMC_NWE
tv(NWE_NE)
t h(NE_NWE)
th(A_NWE)
th(BL_NWE)
tv(Data_NE)
tw(NE)
ai14990
FSMC_NADV(1)
t v(NADV_NE)
tw(NADV)



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