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STM32F101XC Datasheet(PDF) 92 Page - STMicroelectronics

Part # STM32F101XC
Description  High-density access line, ARM-based 32-bit MCU with 256 to 512 KB Flash, 9 timers, 1 ADC and 10 communication interfaces
PDF  106 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F101XC Datasheet(HTML) 92 Page - STMicroelectronics

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Electrical characteristics
STM32F101xC, STM32F101xD, STM32F101xE
92/106
Doc ID 14610 Rev 7
IDDVREF+
DAC DC current consumption
in quiescent mode (Standby
mode)
220
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs.
IDDA
DAC DC current consumption
in quiescent mode (Standby
mode)
380
µA
With no load, middle code
(0x800) on the inputs.
480
µA
With no load, worst code
(0xF1C) at VREF+ = 3.6 V in
terms of DC consumption on
the inputs.
DNL(3)
Differential non linearity
Difference between two
consecutive code-1LSB)
±0.5
LSB
Given for the DAC in 10-bit
configuration.
±2
LSB
Given for the DAC in 12-bit
configuration.
INL(3)
Integral non linearity (difference
between measured value at
Code i and the value at Code i
on a line drawn between Code
0 and last Code 1023)
±1
LSB
Given for the DAC in 10-bit
configuration.
±4
LSB
Given for the DAC in 12-bit
configuration.
Offset(3)
Offset error
(difference between measured
value at Code (0x800) and the
ideal value = VREF+/2)
±10
mV
Given for the DAC in 12-bit
configuration.
±3
LSB
Given for the DAC in 10-bit at
VREF+ = 3.6 V.
±12
LSB
Given for the DAC in 12-bit at
VREF+ = 3.6 V.
Gain error(3)
Gain error
±0.5
%
Given for the DAC in 12bit
configuration.
tSETTLING
(3)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final value
±1LSB
34
µs
CLOAD  50 pF, RLOAD  5k
Update rate(3)
Max frequency for a correct
DAC_OUT change when small
variation in the input code (from
code i to i+1LSB)
1MS/s CLOAD  50 pF, RLOAD  5k
tWAKEUP
(3)
Wakeup time from off state
(Setting the ENx bit in the DAC
Control register)
6.5
10
µs
CLOAD  50 pF, RLOAD  5k
input code between lowest and
highest possible ones.
PSRR+ (2)
Power supply rejection ratio (to
VDDA) (static DC measurement
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1.
Guaranteed by characterization, not tested in production.
2.
Guaranteed by design, not tested in production.
3.
Guaranteed by characterization, not tested in production.
Table 57.
DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max(1)
Unit
Comments



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