ST7263BEx datasheet(119/186 Pages) STMICROELECTRONICS

119 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

119/186

I²C Status register 1 (SR1)

Reset value: 0000 0000 (00h)

EVF

TRA

BUSY

BTF

ADSL

M/SL

Read only

7 EVF Event flag

This bit is set by hardware as soon as an event occurs. It is cleared by software

reading SR2 register in case of error event or as described in Figure 48. It is also

cleared by hardware when the interface is disabled (PE=0).

0: No event

1: One of the following events has occurred:

●

BTF=1 (Byte received or transmitted)

●

ADSL=1 (Address matched in Slave mode while ACK=1)

●

SB=1 (Start condition generated in Master mode)

●

AF=1 (No acknowledge received after byte transmission)

●

STOPF=1 (Stop condition detected in Slave mode)

●

ARLO=1 (Arbitration lost in Master mode)

●

BERR=1 (Bus error, misplaced Start or Stop condition detected)

●

Address byte successfully transmitted in Master mode.

6 Reserved. Forced to 0 by hardware.

5 TRA Transmitter/Receiver.

When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared

automatically when BTF is cleared. It is also cleared by hardware after detection of

Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface

is disabled (PE=0).

0: Data byte received (if BTF=1)

1: Data byte transmitted

4 BUSY Bus busy.

This bit is set by hardware on detection of a Start condition and cleared by

hardware on detection of a Stop condition. It indicates a communication in progress

on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.

0: No communication on the bus

1: Communication ongoing on the bus

Note: The BUSY flag is NOT updated when the interface is disabled (PE=0). This

can have consequences when operating in Multimaster mode; i.e. a second

active I2C master commencing a transfer with an unset BUSY bit can cause

a conflict resulting in lost data. A software workaround consists of checking

that the I2C is not busy before enabling the I2C Multimaster cell.

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