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ST7263BEx Datasheet(PDF) 126 Page - STMicroelectronics |
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ST7263BEx Datasheet(HTML) 126 Page - STMicroelectronics |
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126 / 186 page  On-chip peripherals ST7263Bxx 126/186 Doc ID 7516 Rev 8 Figure 50. ADC block diagram Digital A/D conversion result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than or equal to VDDA (high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication. If input voltage (VAIN) is lower than or equal to VSSA (low-level voltage reference) then the conversion result in the DR register is 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register. The accuracy of the conversion is described in the parametric section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the allotted time. A/D conversion phases The A/D conversion is based on two conversion phases as shown in Figure 51: ● Sample capacitor loading [duration: tLOAD] During this phase, the VAIN input voltage to be measured is loaded into the CADC sample capacitor. ● A/D conversion [duration: tCONV] During this phase, the A/D conversion is computed (8 successive approximations cycles) and the CADC sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy. While the ADC is on, these two phases are continuously repeated. At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behavior is that it minimizes the current consumption on the analog pin in case of single input channel measurement. CH2 CH1 CH3 COCO 0 ADON 0 CH0 ADCCSR AIN0 AIN1 ANALOG TO DIGITAL CONVERTER AINx ANALOG MUX RADC CADC D2 D1 D3 D7 D6 D5 D4 D0 ADCDR 4 DIV 4 fADC fCPU HOLD CONTROL |
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