STM32W108HB datasheet(137/179 Pages) STMICROELECTRONICS

137 / 179 page

STM32W108CB, STM32W108HB

Analog-to-digital converter

Doc ID 16252 Rev 2

137/179

9.2

Interrupts

The ADC has its own ARM® Cortex-M3 vectored interrupt with programmable priority. The

ADC interrupt is enabled by writing the INT_ADC bit to the INT_CFGSET register, and

cleared by writing the INT_ADC bit to the INT_CFGCLR register. Section 10: Interrupts on

page 143 describes the interrupt system in detail.

Four kinds of ADC events can generate an ADC interrupt, and each has a bit flag in the

INT_ADCFLAG register to identify the reason(s) for the interrupt:

●

INT_ADCOVF – an ADC conversion result was ready but the DMA was disabled (DMA

buffer overflow).

●

INT_ADCSAT– the gain correction multiplication exceeded the limits for a signed 16-bit

number (gain saturation).

●

INT_ADCULDFULL – the DMA wrote to the last location in the buffer (DMA buffer full).

●

INT_ADCULDHALF – the DMA wrote to the last location of the first half of the DMA

buffer (DMA buffer half full).

Bits in INT_ADCFLAG may be cleared by writing a 1 to their position.

The INT_ADCCFG register controls whether or not INT_ADCFLAG bits actually request the

ARM® Cortex-M3 ADC interrupt; only the events whose bits are 1 in INT_ADCCFG can do

so.

For non-interrupt (polled) ADC operation set INT_ADCCFG to zero, and read the bit flags in

INT_ADCFLAG to determine the ADC status.

Note:

When making changes to the ADC configuration it is best to disable the DMA beforehand. If

this isn’t done it can be difficult to determine at which point the sample data in the DMA

buffer switch from the old configuration to the new configuration. However, since the ADC

will be left running, if it completes a conversion after the DMA is disabled, the INT_ADCOVF

flag will be set. To prevent these unwanted DMA buffer overflow indications, clear the

INT_ADCOVF flag immediately after enabling the DMA, preferably with interrupts off.

Disabling the ADC in addition to the DMA is often undesirable because of the additional

analog startup time when it is re-enabled.

Table 20.

Offset and gain correction (ADC_HVSELn=1)

Calculation Type

Corrected Sample

Absolute Voltage

Offset corrected

Offset and gain

corrected using

VREF, normalized to

VREF

Offset and gain

corrected using

VDD_PADSA,

normalized to

VDD_PADSA

)

(

VREF

−

)

(

)

(

VREF

−

)

(

VREF

)

(

)

(

VREF

PADSA

VDD

VREF

−

)

(

PADSA

VDD

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