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STM32W108HB Datasheet(PDF) 140 Page - STMicroelectronics |
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STM32W108HB Datasheet(HTML) 140 Page - STMicroelectronics |
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140 / 179 page  Analog-to-digital converter STM32W108CB, STM32W108HB 140/179 Doc ID 16252 Rev 2 9.3.5 ADC DMA status register (ADC_DMASTAT) Address offset: 0xD014 Reset value: 0x0000 0000 9.3.6 ADC DMA begin address register (ADC_DMABEG) Address offset: 0xD018 Reset value: 0x2000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC_ DMAR ST ADC_ DMAA UTOW RAP ADC_ DMAL OAD rw rw rw rw rw rw rw rw rw rw rw w rw rw rw rw [4] ADC_DMARST: Write 1 to reset the ADC DMA. This bit auto-clears. [1] ADC_DMAAUTOWRAP: Selects DMA mode. 0: Linear mode, the DMA stops when the buffer is full. 1: Auto-wrap mode, the DMA output wraps back to the start when the buffer is full. [0] ADC_DMALOAD: Loads the DMA buffer. Write 1 to start DMA (writing 0 has no effect). Cleared when DMA starts or is reset. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC_D MAOVF ADC_D MAACT rw rw rw rw rw rw rw rw rw rw rw rw rw rw r r [1] ADC_DMAOVF: DMA overflow: occurs when an ADC result is ready and the DMA is not active. Cleared by DMA reset. [0] ADC_DMAACT: DMA status: reads 1 if DMA is active. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADC_DMABEG rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [12:0] ADC_DMABEG: ADC buffer start address. Caution: this must be an even address - the least significant bit of this register is fixed at zero by hardware. |
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