PIC18F8722-ESLASHPTSQTP datasheet(65/446 Pages) MICROCHIP

65 / 446 page

DS39646C-page 63

PIC18F8722 FAMILY

5.0

MEMORY ORGANIZATION

There are three types of memory in PIC18 Enhanced

microcontroller devices:

• Program Memory

• Data RAM

• Data EEPROM

As Harvard architecture devices, the data and program

memories use separate busses; this allows for concur-

rent access of the two memory spaces. The data

EEPROM, for practical purposes, can be regarded as

a peripheral device, since it is addressed and accessed

through a set of control registers.

Additional detailed information on the operation of the

Flash program memory is provided in Section 6.0

“Flash

Program

Memory”.

Data

EEPROM

discussed separately in Section 8.0 “Data EEPROM

Memory”.

5.1

Program Memory Organization

PIC18 microcontrollers implement a 21-bit program

counter, which is capable of addressing a 2-Mbyte

program memory space. Accessing a location between

the upper boundary of the physically implemented

memory and the 2-Mbyte address will return all ‘0’s (a

NOP

instruction).

The PIC18F6527 and PIC18F8527 each have 48 Kbytes

of Flash memory and can store up to 24,576 single-word

instructions.

The PIC18F6622 and PIC18F8622 each have 64 Kbytes

of Flash memory and can store up to 32,768 single-word

instructions.

The PIC18F6627 and PIC18F8627 each have 96 Kbytes

of Flash memory and can store up to 49,152 single-word

instructions.

The

PIC18F6722

and

PIC18F8722

each

have

128 Kbytes of Flash memory and can store up to

65,536 single-word instructions.

PIC18 devices have two interrupt vectors. The Reset

vector address is at 0000h and the interrupt vector

addresses are at 0008h and 0018h.

The program memory map for the PIC18F8722 family

of devices is shown in Figure 5-1.

5.1.1

PIC18F8527/8622/8627/8722

PROGRAM MEMORY MODES

PIC18F8527/8622/8627/8722 devices differ signifi-

cantly from their PIC18 predecessors in their utilization

of program memory. In addition to available on-chip

Flash program memory, these controllers can also

address up to 2 Mbytes of external program memory

through the external memory interface. There are four

distinct operating modes available to the controllers:

• Microprocessor (MP)

• Microprocessor with Boot Block (MPBB)

• Extended Microcontroller (EMC)

• Microcontroller (MC)

The program memory mode is determined by setting

the two Least Significant bits of the Configuration

(see Section 25.1 “Configuration Bits” for additional

details on the device Configuration bits).

The program memory modes operate as follows:

•The Microprocessor Mode permits access only

to external program memory; the contents of the

on-chip Flash memory are ignored. The 21-bit

program counter permits access to a 2-Mbyte

linear program memory space.

• The Microprocessor with Boot Block Mode

accesses on-chip Flash memory from the boot

block. Above this, external program memory is

accessed all the way up to the 2-Mbyte limit.

Program execution automatically switches

between the two memories as required. The boot

block is configurable to 1, 2 or 4 Kbytes.

• The Microcontroller Mode accesses only

on-chip Flash memory. Attempts to read above the

physical limit of the on-chip Flash (0BFFFh for the

PIC18F8527, 0FFFFh for the PIC18F8622,

17FFFh for the PIC18F8627, 1FFFFh for the

PIC18F8722) causes a read of all ‘0’s (a NOP

instruction).

The Microcontroller mode is also the only operating

mode available to PIC18F6527/6622/6627/6722

devices.

•The Extended Microcontroller Mode allows

access to both internal and external program

memories as a single block. The device can

access its entire on-chip Flash memory; above

this, the device accesses external program

memory up to the 2-Mbyte program space limit.

As with Boot Block mode, execution automatically

switches between the two memories as required.

In all modes, the microcontroller has complete access

to data RAM and EEPROM.

Figure 5-2 compares the memory maps of the different

program memory modes. The differences between

on-chip and external memory access limitations are

more fully explained in Table 5-1.

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