PIC18F2221 datasheet(156/402 Pages) MICROCHIP

156 / 402 page

PIC18F2221/2321/4221/4321 FAMILY

DS39689F-page 156

17.4.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The PWM duty cycle is

calculated by the following equation.

EQUATION 17-2:

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not copied into

CCPR1H until a match between PR2 and TMR2 occurs

(i.e., the period is complete). In PWM mode, CCPR1H

is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation. When the CCPR1H and 2-bit latch match

TMR2, concatenated with an internal 2-bit Q clock or

two bits of the TMR2 prescaler, the CCP1 pin is

cleared. The maximum PWM resolution (bits) for a

given PWM frequency is given by the following

equation.

EQUATION 17-3:

17.4.3

PWM OUTPUT CONFIGURATIONS

The P1M<1:0> bits in the CCP1CON register allow one

of four configurations:

• Single Output

• Half-Bridge Output

• Full-Bridge Output, Forward mode

• Full-Bridge Output, Reverse mode

The Single Output mode is the standard PWM mode

discussed in Section 17.4 “Enhanced PWM Mode”.

The Half-Bridge and Full-Bridge Output modes are

covered in detail in the sections that follow.

The general relationship of the outputs in all

configurations is summarized in Figure 17-2.

TABLE 17-2:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

(

)

PWM Resolution (max) =

FOSC

FPWM

log

log(2)

bits

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz

156.25 kHz

312.50 kHz

416.67 kHz

Timer Prescaler (1, 4, 16)

41111

PR2 Value

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

6.58

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