PCIMX515CJM6C datasheet(126/184 Pages) FREESCALE

126 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

126

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

•

The terms WL and BL refer to Word Length (WL) and Byte Length

(BL).

•

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

3.7.15.4

SSI Receiver Timing with External Clock

Figure 92. SSI Receiver External Clock Timing Diagram

Synchronous External Clock Operation

SS44

SRXD setup before (Tx) CK falling

10.0

—

SS45

SRXD hold after (Tx) CK falling

2.0

—

SS46

SRXD rise/fall time

—

6.0

Table 91. SSI Transmitter Timing with External Clock (continued)

Parameter

Min

Max

Unit

SS24

SS34

SS35

SS30

SS28

SS26

SS25

SS23

SS40

SS22

SS32

SS36

SS41

TXC

(Input)

TXFS (bl)

(Input)

TXFS (wl)

(Input)

RXD

(Input)

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