PCIMX515CJM6C datasheet(124/184 Pages) FREESCALE

124 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

124

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables

and in the figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

•

The terms WL and BL refer to Word Length (WL) and Byte Length

(BL).

•

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

SS48

Oversampling clock high period

6.0

—

SS49

Oversampling clock rise time

—

3.0

SS50

Oversampling clock low period

6.0

—

SS51

Oversampling clock fall time

—

3.0

Table 90. SSI Receiver Timing with Internal Clock (continued)

Parameter

Min

Max

Unit

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