AT90SCR100 datasheet(278/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

must be configured before enabling the HSSPI Controller. Any attempt at modifying the HSSPI

Clock frequency once the HSSPI Controller is enabled will not affect it. The HSSPICFG.MSTR

bit selects either Master or Slave operations. The HSSPI Master initiates the communication

cycle after pulling low the HSSS line of the desired Slave.

The Master and Slave prepare the data to be sent using their respective shift registers or using

the internal DPRAM (according to the HSSPICFG.DPRAM bit), and the Master generates the

required clock pulses on the HSSCK line to exchange data. Data is always shifted from Master

to Slave on the Master Out - Slave In, HSMOSI line, and from Slave to Master on the Master In -

Slave Out, HSMISO line, simultaneously.

Figure 21-2.

HSSPI Master - Slave Interconnection

The DPRAM stores two 16 Bytes buffers for transmission and two 16 Bytes buffers for reception.

21.2.1

HSSPI Controller Configured as a Master

When configured as a Master, the HSSPI interface has no automatic control of the HSSS line.

This must be handled by software before starting the communication.

21.2.1.1

One byte sending using shift register (without DPRAM)

When the DPRAM is not activated (HSSPICFG.DPRAM bit cleared) and a byte is written to the

HSSPI Transmit Data Register (HSSPITDR register), the hardware shifts the 8 bits (MSB first)

into the Slave and receives a byte from the Slave simultaneously. After shifting one byte, the

Byte Transfer Done flag (HSSPIIR.BTD) is set. If global interrupt and the HSSPIIER.BTDIE bit

have been previously set, an interrupt is generated.

At this stage, the Master can read the HSSPIRDR register to retrieve the byte sent by the other

device. The HSSPIIR.BTD flag must then be cleared by software.

The figure below illustrates the way the HSSPI works when configured as a Master without

DPRAM mode.

Master HSSPI

Clock Generator

8 Bit Shift Register

Msb

Lsb

Master

Slave

8 Bit Shift Register

Msb

Lsb

HSSCK

HSMOSI

HSMISO

Chip as Master

Chip as Slave

AT90SCR100 Datasheet(PDF) 278 Page - ATMEL Corporation

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