AT90SCR100 datasheet(279/433 Pages) ATMEL

279 / 433 page

279

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 21-3.

HSSPI - Master without DPRAM operation

21.2.1.2

Buffer sending with DPRAM and HSSPIDMA (DPRAM mode)

When the DPRAM is activated (HSSPICFG.DPRAM bit set), the data to be sent must be written

to one of the internal DPRAM buffers using the HSSPIDMA. To do so, use the HSSPIDMA

mechanism to copy HSSPIDMAB bytes from RAM to DPRAM. It is not possible to copy more

than 16 bytes per copy. The DPRAM targeted by the copy is totally transparent to the user.

Once this is done, the number of bytes to be transmitted is written to the HSSPICNT register.

The HSSPI interface will start to shift this number of bytes from the master to the slave and from

the slave to the master simultaneously. If the HSSPISR.TXBUFE = 1, new data can be copied in

the second buffer using HSSPIDMA again. After shifting all the bytes of one buffer, the Byte

Transfer Done flag (HSSPIIR.BTD) is set. If the HSSPI interrupt enable bit and the HSSPI-

IER.BTDIE bit have been previously set, an interrupt is generated.

Clear BTD (HSSPIIR)

(mandatory if IRQ mode)

Data to receive?

Configure SPI Guard Time

(HSSPIGTR)

Configure SPICK frequency

(HSSPIFG)

Read data from HSSPIRDR

YES

Wait HSSPICKRDY

Write data to send

into HSSPITDR

Configure CPOL,

CPHA, MSTR=1,

SPIEN, DPRAM=0,

BTDIE (if IRQ mode)

Wait BTD (HSSPIIR)

AT90SCR100 Datasheet(PDF) 279 Page - ATMEL Corporation