AT90SCR100 datasheet(280/433 Pages) ATMEL

280 / 433 page

280

TPR0327AY–SMS–30Jan09

AT90SCR100

At this point, the Master can copy the received data from reception DPRAM into RAM, using

HSSPIDMA. The HSSPIIR.BTD flag must then be cleared by software.

If the HSSPIIR.BTD is set and the next buffer becomes full, the HSSPIIR.RCVOF is set. If the

HSSPI interrupt enable bit and the HSSPIIER.RCVOFIE bit have been previously set, an inter-

rupt is generated.

The figure below illustrates the way the HSSPI works when configured as a Master with

DPRAM/HSSPIDMA.

Figure 21-4.

SPI - Master with DPRAM/HSSPIDMA activated

Configure SPICK frequency

(HSSPICFG)

Data to receive?

Configure SPI Guard Time

(HSSPIGTR)

Configure CPOL, CPHA, MSTR=1,

SPIEN, DPRAM=1, BTDIE (if IRQ

mode)

Wait SPICKRDY (HSSPISR)

Read SPICNT

Start copy of received data into

RAM using HSSPIDMA.

Read received data directly in RAM

Wait BTD (HSSPIIR)

Clear BTD (HSSPIIR)

YES

nb_data to send or

receive>16?

TXBUFE?

(HSSPISR)

Init RAM data and HSSPIDMA

Copy data into DPRAM

Write 16 in HSSPICNT

Prepare RAM and HSSPIDMA

Copy 16 or nb_data left data

into DPRAM.

Write 16 or nb_data left in HSSPICNT

YES

Init RAM data and HSSPIDMA

Copy data into DPRAM

Write 16 in HSSPICNT

Prepare RAM and HSSPIDMA

Copy nb_data left data into DPRAM.

Write nb_data left in HSSPICNT

AT90SCR100 Datasheet(PDF) 280 Page - ATMEL Corporation

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