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AT90SCR100 Datasheet(PDF) 342 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 342 Page - ATMEL Corporation |
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342 / 433 page ![]() 342 TPR0327AY–SMS–30Jan09 AT90SCR100 This bit is set and cleared by software. Set this bit to perform AES encryption when setting AESGO. Clear this bit to perform AES decryption when setting AESGO. • Bit 0 - AESGO : AES Run Bit This bit is set by software and cleared by hardware. Set this bit to run AES operation specified by the other register settings. This bit is cleared by hardware when the AES operation is complete. If this bit is equal to one, then the AES block is running and busy. 25.3.2 AESACR - AES Access Control Register • Bit 7..4 - Reserved Bits These bits are reserved for future use. • Bit 3 - XOR : XOR Mode This bit is set and cleared by software. This bit has no influence if the KD bit is set. When this bit is cleared, writing new data in AESDR will copy the data in AES data memory, in accordance with AESADDR register. When this bit is set and new data is written into the AESDR, the data to the AES data memory, according to AESADDR register, will be ‘xored’ with the new data. This is useful when perform- ing a CBC algorithm, or MAC generation. • Bit 2 - MANINC : Manual Increment bit This bit is a write-only bit and always reads as ‘0’. This bit can only be set. Setting this bit will increment the AESADDR register by one. • Bit 1 - AUTOINC : Automatic Increment Bit This bit is set and cleared by software. If this bit is set, writing new data in th AESDR register will automatically increment the AESADDR register by one, after the new data is loaded. The mechanism of automatic AESDR changes are active, which means that the AESDR contents will be updated with the data pointed by the new AESADDR register value. If this bit is cleared, the automatic increment is disabled. • Bit 0 - KD : Key/Data bit Bit 7654 3 2 1 0 $0079 - - - - XOR MANINC AUTOINC KD AESACR Read/write RRRR R/W W R/W R/W Initial value 0000 0 0 1 0 0x02 When performing a write operation to the AESACR register, with this bit set, it is not possible to change the state of the other register bits. This prevents the user accidentally changing the functional operation of the AES during a manual incre- ment operation. Note |
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