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AT90SCR100 Datasheet(PDF) 340 Page - ATMEL Corporation |
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AT90SCR100 Datasheet(HTML) 340 Page - ATMEL Corporation |
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340 / 433 page ![]() 340 TPR0327AY–SMS–30Jan09 AT90SCR100 25.2.1 Memory Organization There are 2 address areas: Key and Data. Internal registers can be observed or modified via the AESADDR and AESDR registers. Below is a way to organize the memory according to an example: Figure 25-2. Example of memory organization Assembly code is available in section “Example. Code Sample” on page 343. All bytes must be reverted in the AES Data and Key memory. This means that the data must be oriented LSB first As memory is reversed, the AES 128Key LSB will start at address #16 and MSB of AES128 key will be at address #31 The result is also inverted in Data internal memory (LSB first). Caution ! Caution ! Caution ! 00010203050607080A0B0C0D0F101112 AES128 Key: 506812A45F08C889B97F5980038B8359 Data To cipher: Ciphered Message: D8F532538289EF7D06B506A4FD5BE9C9 AES_Key 12 11 10 0F 0D 0C 0B 0A 08 07 06 05 03 02 01 00 #0 #15 #16 #31 AES_Data 59 83 8B 03 80 59 7F B9 89 C8 08 5F A4 12 68 50 #00 #15 AES_Result This is what can be read in the Data register after AES Run of AES128 encryption C9 E9 5B FD A4 06 B5 06 7D EF 89 82 53 32 F5 D8 #00 #15 |
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