AT90SCR100 datasheet(339/433 Pages) ATMEL

339 / 433 page

339

TPR0327AY–SMS–30Jan09

AT90SCR100

25. AES 128/256 Engine

To support all the security needs and requirements of embedded systems, the AT90SCR100

features a hardware AES engine. It provides an efficient and easy way to perform standard cryp-

tographic calculus.

25.1

Features

• 128 and 256 bits key length

• Encryption and Decryption algorithm

• Supports ECB, CBC, and MAC algorithms

• Specific Encryption/Decryption key generation for optimized revet algorithm

• Auto-incremented pointer register on data write for fast data loading

• Interrupt generation on calculus completion

25.2

Overview

The AES module of the AT90SCR100 includes an internal memory, dedicated to AES manage-

ment. These registers are not directly accessible from the AVR core, and the user must use a

specific interface to write both key and data.

The AES module can only manage one data block of 128 bits at a time.

The figure below shows how to access the internal memory of the AES block:

Figure 25-1.

AES Block Interface

AES Key Register

AES Engine

AES Control

System

AES Block

AES Data Register

Internal Memory

0x00

0x31

0x15

AESDR

AESADDR

AESACR

Address Decoder

AESACR.KD

AESACR.KD=0

AESACR.KD=1

AES Interrupt signal

AT90SCR100 Datasheet(PDF) 339 Page - ATMEL Corporation

AT90SCR100 Datasheet(HTML) 339 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL