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ASDL-3023 Datasheet(PDF) 18 Page - Lite-On Technology Corporation |
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ASDL-3023 Datasheet(HTML) 18 Page - Lite-On Technology Corporation |
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18 / 26 page ![]() Appendix B: PCB Layout Suggestion TheeffectsofEMIandpowersupplynoisecanpotentially reducethesensitivityofthereceiver,resultinginreduced linkdistance.ThePCBlayoutplayedanimportantroleto obtainagoodPSRRandEMimmunityresultingingood electricalperformance.Thingstonote: 1. The ground plane should be continuous under the part,butshouldnotextendundertheshieldtrace. 2. Theshieldtraceisawide,lowinductancetraceback tothesystemground.CX1,CX2,CX3,CX4andCX5are optionalsupplyfiltercapacitors;theymaybeleftoutif acleanpowersupplyisused. 3. VLED can be connected to either unfiltered or unregulated power supply. The bypass capacitors should be connection before the current limiting resistor R2 respectively. In a noisy environment, including capacitor CX3and CX4 can enhance supply rejection.CX3thatisgenerallyaceramiccapacitorof lowinductanceprovidingawidefrequencyresponse whileCX4istantalumcapacitorofbigvolumeandfast frequency response.The use of a tantalum capacitor ismorecriticalontheVLEDline,whichcarriesahigh current. 4. VCC pin can be connected to either unfiltered or unregulated power supply.The Resistor, R1 together withthecapacitors,CX1andCX2actsasthelowpass filter. 5. IOVCC is connected to the ASIC voltage supply or theVCCsupply.Thecapacitor,CX5actsasthebypass capacitor. 6. Preferably a multi-layered board should be used to provide sufficient ground plane. Use the layer underneath and near the transceiver module as Vcc, and sandwich that layer between ground connected board layers. The diagram below demonstrate an exampleofa4layerboard: • TopLayer: Connectthemetalshieldand modulegroundpintobottom groundlayer; Placethebypasscapacitorswithin 0.5cmfromtheVCCandground pinofthemodule. • Layer2: Criticalgroundplanezone.3 cminalldirectionaroundthe module.Connecttoaclean, noiselessgroundnode(eg bottomlayer). • Layer3: Keepdatabusawayfromcritical groundplanezone. • Bottomlayer: Groundlayer.Groundnoise<75 mVp-p.Shouldbeseparatedfrom groundusedbynoisysources. Theareaunderneaththemoduleatthesecondlayer,and 3cminalldirectionaroundthemoduleisdefinedasthe criticalgroundplanezone.Thegroundplaneshouldbe maximizedinthiszone.RefertoapplicationnoteAN1114 ortheAvagoTechnologiesIrDADataLinkDesignGuide fordetails.Thelayoutbelowisbasedona2-layerPCB. Top Layer Bottom Layer Layer 3 Top Layer Layer 2 Bottom Layer (GND) Noise sources to be placed as far away from the transceiver as possible Legend: ground via CX3 CX4 CX1 CX2 R 1 R 2 CX5 |
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