ST7568 datasheet(17/73 Pages) SITRONIX

17 / 73 page

ST7568

Ver 2.2

17/73

2008/01/04

IMS=

” L “, P/S=” L “:I

2C Interface

The I

2C interface send RAM data and executes the commands sent via the I2C Interface. It could send data it to the RAM.

The I

2C Interface is two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA)

and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be

initiated only when the bus is not busy.

BIT TRANSFER

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of

the clock pulse because changes in the data line at this time will be interpreted as a control signal. Bit transfer is illustrated

in Fig.3.

START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock

is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined

as the STOP condition (P). The START and STOP conditions are illustrated in Fig.4.

SYSTEM CONFIGURATION

The system configuration is illustrated in Fig.5.

· Transmitter: the device, which sends the data to the bus

· Master: the device, which initiates a transfer, generates clock signals and terminates a transfer

· Slave: the device addressed by a master

· Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message

· Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed

to do so and the message is not corrupted

· Synchronization: procedure to synchronize the clock signals of two or more devices.

ACKNOWLEDGE

Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the

transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is

addressed must generate an acknowledge after the reception of each byte. A master receiver must also generate an

acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that

acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during

the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master

receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been

clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a

STOP condition. Acknowledgement on the I

2C Interface is illustrated in Fig.6.

ST7568 Datasheet(PDF) 17 Page - Sitronix Technology Co., Ltd.