ST7568 datasheet(21/73 Pages) SITRONIX

21 / 73 page

ST7568

Ver 2.2

21/73

2008/01/04

DISPLAY DATA RAM (DDRAM)

The ST7568 contains a 68X102X2 bit static RAM that stores the display data. The display data RAM store the dot data for

the LCD. It has a 68(8 pageX8 bit +1 pageX3 bit +1 pageX1 bit) X102 X2. There is a direct correspondence between

X-address and column output number. It is 68-row by 102-column addressable array. Each pixel can be selected when the

page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines (0~63 COM) and 8th page with

three line (D0 ~D2)(64~ 66 COM) and 9th page with a single line (D0 only)(67 row

—COMS (ICON). Data is read from or

written to the 8 lines of each page directly through D0 to D7. The display data of D0 to D7 from the microprocessor

correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since

the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed

without causing the LCD flicker.

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 6. It incorporates 4-bit Page

Address register changed by only the

“Set Page” instruction. Page Address 9 is a special RAM area for the icons and

display data D0 is only valid.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line

Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of

on-chip RAM as shown in figure 10. It incorporates 7-bit Line Address register changed by only the initial display line

instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line

counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display

data latch circuit. When icon is selected by setting icon page address, display data of icons are not scrolled because the

MPU cannot access Line Address of icons.

Column Address Circuit

Column Address Circuit has an 8-bit preset counter that provides Column Address to the Display Data RAM as shown in

figure11. The display data RAM column address is specified by the Column Address Set command. The specified column

address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed

continuously.

segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing MX select instruction. Refer to the

following figure 12.

SEG Output

SEG0

SEG101

“0”

seg0

à Segment Address à seg101

“1”

seg101

ß Segment Address ß seg0

Com Output

SEG Output

Com0

Com66

Coms

“0”

com0

à Common Address à com66 Coms

“1”

com66

ß Common Address ß com0 Coms

COM Scan Direction

Status

1/65 DUTY

1/68 DUTY

Normal

Reverse

COM0

à COM63

COM63

à COM0

COM0

à COM66

COM66

à COM0

Common output pins

Duty

Com [0:31]

Com [32:34]

Com [35:66]

Coms

Com [0:66]

Coms

1/68

Com [66:0]

Coms

Com [0:31]

Reverse

Com [32:63]

Coms

1/65

Com [63:32]

Reverse

Com [31:0]

Coms

ST7568 Datasheet(PDF) 21 Page - Sitronix Technology Co., Ltd.

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