| Electronic Components Datasheet Search |
|
dsPIC33FJ32GS608 Datasheet(PDF) 255 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
dsPIC33FJ32GS608 Datasheet(HTML) 255 Page - Microchip Technology |
|
255 / 416 page ![]() 2009 Microchip Technology Inc. Preliminary DS70591B-page 255 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 17.0 QUADRATURE ENCODER INTERFACE (QEI) MODULE This chapter describes the Quadrature Encoder Inter- face (QEI) module and associated operational modes. The QEI module provides the interface to incremental encoders for obtaining mechanical position data. The operational features of the QEI include: • Three input channels for two phase signals and index pulse • 16-bit up/down position counter • Count direction status • Position Measurement (x2 and x4) mode • Programmable digital noise filters on inputs • Alternate 16-bit Timer/Counter mode • Quadrature Encoder Interface interrupts These operating modes are determined by setting the appropriate bits, QEIM<2:0> in (QEIxCON<10:8>). Figure 17-1 depicts the Quadrature Encoder Interface block diagram. FIGURE 17-1: QUADRATURE ENCODER INTERFACE BLOCK DIAGRAM (x = 1 OR 2) Note 1: This data sheet summarizes the features of the dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Quadrature Encoder Interface (QEI)” (DS70208) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be avail- able on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. Note: An ‘x’ used in the names of pins, control/ status bits and registers denotes a particular Quadrature Encoder Interface (QEI) module number (x = 1 or 2). 16-bit Up/Down Counter Comparator/ Max Count Register QEAx(1) INDXx(1) 1 Up/Down Existing Pin Logic UPDNx 3 QEBx(1) QEIM<2:0> Mode Select 3 (POSxCNT) (MAXxCNT) PCDOUT QExIF Event Flag Reset Equal 2 TCY 1 0 TQCS TQCKPS<1:0> 2 Q Q D CK TQGATE QEIM<2:0> 1 0 Sleep Input 0 1 UPDN_SRC QEIxCON<11> Zero Detect Synchronize Det 1, 8, 64, 256 Prescaler Quadrature Encoder Interface Logic Programmable Digital Filter Programmable Digital Filter Programmable Digital Filter Note 1: The QEI1 module can be connected to the QEA1/QEB1/INDX1 or AQEA1/AQEB1/AINDX1 pins, which are controlled by clearing or setting the ALTQIO bit in the FPOR Configuration register. See Section 24.0 “Special Features” for more information. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |