DSPIC33FJ32GS608 datasheet(192/416 Pages) MICROCHIP

192 / 416 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591B-page 192

Preliminary

 2009 Microchip Technology Inc.

OSCCON: OSCILLATOR CONTROL REGISTER(1)

U-0

R-y

U-0

R/W-y

—COSC<2:0>

—NOSC<2:0>(2)

bit 15

bit 8

R/W-0

U-0

R-0

U-0

R/C-0

U-0

R/W-0

CLKLOCK

—LOCK

—CF

—

OSWEN

bit 7

bit 0

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

000 = Fast RC oscillator (FRC)

001 = Fast RC oscillator (FRC) with PLL

010 = Primary oscillator (XT, HS, EC)

011 = Primary oscillator (XT, HS, EC) with PLL

100 = Secondary oscillator (SOSC)

101 = Low-Power RC oscillator (LPRC)

110 = Fast RC oscillator (FRC) with divide-by-16

111 = Fast RC oscillator (FRC) with divide-by-n

bit 11

Unimplemented: Read as ‘0’

bit 10-8

NOSC<2:0>: New Oscillator Selection bits(2)

000 = Fast RC oscillator (FRC)

001 = Fast RC oscillator (FRC) with PLL

010 = Primary oscillator (XT, HS, EC)

011 = Primary oscillator (XT, HS, EC) with PLL

100 = Secondary oscillator (SOSC)

101 = Low-Power RC oscillator (LPRC)

110 = Fast RC oscillator (FRC) with divide-by-16

111 = Fast RC oscillator (FRC) with divide-by-n

bit 7

CLKLOCK: Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01):

1 = Clock switching is disabled, system clock source is locked

0 = Clock switching is enabled, system clock source can be modified by clock switching

bit 6

Unimplemented: Read as ‘0’

bit 5

LOCK: PLL Lock Status bit (read-only)

1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied

0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4

Unimplemented: Read as ‘0’

bit 3

CF: Clock Fail Detect bit (read/clear by application)

1 = FSCM has detected clock failure

0 = FSCM has not detected clock failure

bit 2-1

Unimplemented: Read as ‘0’

bit 0

OSWEN: Oscillator Switch Enable bit

1 = Request oscillator switch to selection specified by NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307)

in the “dsPIC33F Family Reference Manual” (available from the Microchip web site) for details.

2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC mode

as a transition clock source between the two PLL modes.

dsPIC33FJ32GS608 Datasheet(PDF) 192 Page - Microchip Technology

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